The present invention relates to floating gate field effect transistor storage device and more particularly to an electrode arrangement for electrically erasing such floating gate device.
References known to the present applicants which may be relevant to the present invention include: U.S. Pat. No. 3,755,721 issued to Frohman-Bentchkowsky; U.S. Pat. No. 3,996,657 issued to Simko et al.; U.S. Pat. No. 4,115,914 issued to Harari; U.S. Pat. No. 4,142,926 issued to Morgan; the publication entitled "Electrically Erasable Buried-Gate Nonvolatile Read-Only Memory" by Neugebauer et al. IEEE Transactions on Electron Devices Vol. ED-24, No. 5, May 1977, pages 613 to 618; and the publication entitled "Technology of a New n-Channel One Transistor EAROM Cell Called SIMOS" by Scheibe et al. IEEE Transactions on Electron Devices Vol. ED-24, No. 5, May 1977, pages 600 through 606.
The above referenced Scheibe publication teaches a stacked gate memory device which takes advantage of the one transistor memory cell and allows for electrical erasing of information stored in the cell. The one transistor cell is desirable since it requires less space on the surface of a silicon substrate so that more information may be stored in a given area. The stored information in such a device may be electrically erased by application of a relatively high voltage, on the order of 50 volts, to the source in the respect to both substrate and gate. To provide the electrically erasable feature, this reference teaches a modified stacked gate configuration in its FIG. 7 which uses additional area on the integrated circuit layout.
The Neugebauer publication provides a small erase gate overlying a floating gate in a two transistor memory cell. Since the erase gate overlies only a portion of the floating gate, capacitive coupling between the erase and floating gate is reduced so that less voltage is required in the erase cycle. Even so, this device requires an erase voltage of 30 to 35 volts.
The above referenced U.S. Pat. No. 3,755,721 provides a good disclosure of the Avalanche Injection technique for charging floating gates in solid state storage devices. However, the only technique taught in that patent for erasing the stored information is exposure of the device to ultraviolet or x-ray radiation.
The above referenced U.S. Pat. No. 3,996,657 employs hot carrier injection of charge through the gate oxide layer to write information on a floating gate. This patent also teaches that, in addition to erasing by exposure to ultraviolet light, electrical erasure can be achieved by application of a large positive voltage to the control gate 20.
The above referenced U.S. Pat. No. 4,115,914 provides a stacked gate arrangement in which the oxide between floating gate and substrate has one portion which is sufficiently thin for generation of tunnel currents. In this device, the typical Avalanche Injection technique is used for writing of information while the tunnel currents are used for erasing.
The above referenced U.S. Pat. No. 4,142,926 teaches a method for producing self-aligned stacked gate structures useful in the programmable read-only memories which employ the one transistor storage cell arrangement.
It can be seen from the above references that it is desirable to employ the one transistor storage cell in programmable read-only memories to achieve the maximum storage density. Likewise, it can be seen from these references that an electrically erasable cell is quite desirable in such memories. While the ultraviolet light erasable cells have proven quite useful, they generally require a special package with a transparent lid and require that the device be physically removed from a circuit board and positioned for exposure to an appropriate light source. While it is known that electrical erasure can be achieved in a stacked gate structure, it is also known that relatively high voltages must be applied, for example to the control gate, to achieve the electrical erasure. These erasure voltages are typically greater than the breakdown voltages of the various nodes within the integrated circuit and thus often lead to destruction of the device or require excessively high currents. A device which would be electrically erasable at a voltage on the order of the write voltage, typically 25 volts, or below would be desirable. The known electrical erasing structures also occupy additional space on the integrated circuits and thereby reduce storage density.